(1) Field of the Invention
The present invention relates to methods of fabricating embedded memory devices, and more particularly, to methods of fabricating an embedded memory device with a stress balance layer so that formation of voids is prevented.
(2) Description of the Prior Art
SRAM cells in the past have been fabricated using six transistors, usually comprises of four N-channel metal oxide semiconductor field effect transistor (MOSFET) devices and two P-channel MOSFET devices. However, to reduce processing costs, the semiconductor industry has been attempting to fabricate smaller chips, where the smaller chips still offer device densities equal to or greater than the counterpart larger semiconductor chips. The attainment of a large number of smaller semiconductor chips on a specific size starting substrate allows the processing cost of a specific chip to be reduced. However, the use of smaller chips for SRAM technology creates problems when attempting to place six transistors on the smaller semiconductor chip. Therefore, SRAM designs have focused on one transistor, 1T-RAM cells, comprised of a single MOSFET device and a capacitor structure. This configuration, featuring a single transistor and a single capacitor, provides the same function as the six transistor design, but requiring less space and, thus, fulfilling the objective of constructing smaller semiconductor chips.
Due to continued improvement in process integration, it is the present trend of the semiconductor industry to fabricate semiconductor integrated circuits that integrate both a memory cell array and high-speed logic circuit elements onto a single chip to form an embedded memory (such as embedded DRAM, embedded 1T-SRAM). The embedded memory simultaneously combines the memory arrays and logic circuits to greatly reduce the circuit area and to increase signal processing speed. For the 1T-RAM process, the capacitor's process needs to complete before the logic process and to be fully compatible with the logic process. Meanwhile, in order to scale down the cell size, having a passing gate overlap the capacitor is necessary in the present design. Because the capacitor's process is finished before the logic process completes, the capacitor will suffer high thermal stress from gate oxide growth, source/drain implantation, and salicide high temperature anneal process. These high thermal annealings will induce voids between the top plate electrode and the top plate electrode's antiflective coating (ARC) layer. The voids will result in a gate to gate short after the transistor gate patterning.
A number of patents address the problem of stress. U.S. Pat. No. 6,136,688 to Lin et al shows a high compressive stress oxide layer to eliminate cracks in a subsequently deposited tensile stress layer such as SiON. U.S. Pat. No. 6,414,376 to Thakur et al discloses a silicon-rich SiN layer that relieves stress in a SiN layer. U.S. Pat. No. 5,883,001 to Jin et al shows a PE-SION or SiN layer having compressive stress with an overlying PSG layer having tensile stress as a stress buffer. U.S. Pat. No. 5,503,882 to Dawson describes a PECVD oxide layer under a TEOS oxide layer where the compressive stress of the PECVD oxide layer offsets the TEOS layer's tensile stress. However, these patents do not deal with the 1T-RAM process, especially buried capacitors. The buried capacitor has a rough topography that can easily induce high stress. The buried capacitor must be formed before the gate transistor and salicide processes which then produce high thermal stress cycling.
U.S. Pat. No. 6,221,794 to Pangrle et al teaches annealing before interlayer dielectric deposition to avoid stress-induced voids. U.S. Pat. No. 5,583,077 to Wang et al discloses that compressive stress appears in a PSG layer if the layer is exposed to humidity for a time before a SiN layer is deposited over it. U.S. Pat. No. 6,468,855 to Leung et al describes stress avoidance by performing high thermal cycles prior to P+/N+ shallow junction formation and salicidation. U.S. Pat. No. 6,287,962 to Lin describes a graded SNO layer where the top of the layer provides an ARC function.